Intel Celeron 2961Y is based on the Haswell architecture. The total of cores is 2 with the threads of 2. The operating base core clock is 1.10 GHz. Turbo-boost is No turbo (per-core). The technology node is 22 nm. L2 Cache is , L3 Cache is 2.00 MB.
Intel Celeron 2961Y supports the socket type of BGA 1168.
The supported type and memory clock is DDR3L-1600 SO-DIMM MHz. The maximum RAM capacity is . The date of release is - Q4/2013.
The official technical specifications of the Intel Celeron 2961Y CPU allow defining to what extent it is fast and efficient in the process and which system requirements for games and operational apps it can fit. Please learn the specs and benchmark results.
Technical specs
| Frequency: | 1.10 GHz | CPU Cores: | 2 | |
| Turbo (1 Core): | No turbo | CPU Threads: | 2 | |
| Turbo (2 Cores): | No turbo | Hyperthreading: | No | |
| Overclocking: | No |
| GPU name: | Intel HD Graphics (Haswell GT1) | |||
| GPU frequency: | 0.20 GHz | GPU (Turbo): | 0.85 GHz | |
| Generation: | 7.5 | DirectX Version: | 11.1 | |
| Execution units: | 10 | Shader: | 80 | |
| Max. Memory: | -- | Max. displays: | 3 | |
| Technology: | 22 nm | Release date: | Q4/2012 | |
| h264: | Decode / Encode | |||
| JPEG: | Decode | |||
| h265 8bit: | No | |||
| h265 10bit: | No | |||
| VP8: | No | |||
| VP9: | No | |||
| VC-1: | Decode | |||
| AVC: | Decode / Encode | |||
| Memory type: | DDR3L-1600 SO-DIMM | Memory channels: | 2 | |
| ECC: | No | PCIe version: | 2.0 | |
| PCIe lanes: | 12 |
| AES-NI: | No |
| TDP: | 11.5 W | Tjunction max.: | -- | |
| TDP up: | -- | TDP down: | -- |
| L3-Cache: | 2.00 MB | Technology: | 22 nm | |
| Architecture: | Haswell | Virtualization: | VT-x | |
| Socket: | BGA 1168 | Release date: | Q4/2013 |
| Used in: | Unknown | |||
Please learn the testing results of the Intel Celeron 2961Y CPU in synthetic benchmarks. These data can define the closest competitor and its current position in the models’ rating. Here are points in modern benchmarks, in which Intel Celeron 2961Y has been tested. Pay attention that the data can differ in testing systems.
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